The present invention generally relates to digitally controlled oscillators (DCOs), and particularly relates to reducing non-monotonic regions in the output response of a DCO.
A DCO generates an output response corresponding to a digital control word input. Ideally, the output response of a DCO monotonically changes in response to a corresponding monotonically changing digital control word input. However, process variations and other anomalies may cause non-monotonic regions in the output response of a conventional DCO. When a DCO operates in a non-monotonic region, its output response does not monotonically increase/decrease in response to a corresponding monotonically increasing/decreasing control word. Instead, breaks occur in the DCO output response. These breaks may cause duplicative regions in the DCO output response, i.e., regions in the DCO output response where different control word values produce the same or nearly the same output response. Duplicative regions in the DCO output response may cause errors or other problems in certain applications.
For example, a DCO conventionally forms an integral part of a Phase-Locked Loop (PLL). When included in a PLL, a DCO is the mechanism by which the PLL adjusts its output phase or frequency. In operation, a PLL attempts to ‘lock’ onto or synchronize itself with an input reference signal. Particularly, a phase detector determines the phase difference between a feedback signal derived from the output of the PLL and a reference signal where the output of the PLL is the DCO output. The output of the phase detector is converted to a digital control word for input to the DCO. In response to the digital control word input, the DCO adjusts its output frequency accordingly. A feedback path formed between the DCO output and the phase detector input causes the PLL to adjust the DCO output frequency until the phase/frequency difference between the reference signal input and the feedback signal is within an acceptable limit. When this occurs, the PLL is said to be locked or synchronized to the reference signal input.
Non-monotonic regions in the DCO output response can increase the phase noise generated by the PLL. Increased phase noise may cause undesirable behavior by circuitry that receives a clock signal generated by the PLL. Particularly, if PLL lock occurs at or near a non-monotonic DCO operating region, PLL phase noise may increase due to unexpected behavior, such as sudden phase jump or the PLL running into a limited cycle when the DCO operates in such a region. A PLL is less likely to cleanly lock onto the phase or frequency of a reference signal input when different control word values input to the DCO cause duplicative regions in the DCO output response.